#include <NUC123.h>

Data Fields
__IO uint32_t	PWRCON

__IO uint32_t	AHBCLK

__IO uint32_t	APBCLK

__IO uint32_t	CLKSTATUS

__IO uint32_t	CLKSEL0

__IO uint32_t	CLKSEL1

__IO uint32_t	CLKDIV

__IO uint32_t	CLKSEL2

__IO uint32_t	PLLCON

__IO uint32_t	FRQDIV

__I uint32_t	RESERVE0

__IO uint32_t	APBDIV

Detailed Description

Definition at line 401 of file NUC123.h.

Field Documentation

CLK_T::AHBCLK

Offset: 0x04 AHB Devices Clock Enable Control Register

Bits	Field	Descriptions
[1]	PDMA_EN	PDMA Controller Clock Enable Control 0 = PDMA peripheral clock Disabled. 1 = PDMA peripheral clock Enabled.
[2]	ISP_EN	Flash ISP Controller Clock Enable Control 0 = Flash ISP peripheral clock Disabled. 1 = Flash ISP peripheral clock Enabled.

Definition at line 762 of file NUC123.h.

CLK_T::APBCLK

Offset: 0x08 APB Devices Clock Enable Control Register

Bits	Field	Descriptions
[0]	WDT_EN	Watchdog Timer Clock Enable Control (Write Protect) 0 = Watchdog Timer clock Disabled. 1 = Watchdog Timer clock Enabled. Note: This bit is write protected bit. Refer to the REGWRPROT register.
[2]	TMR0_EN	Timer0 Clock Enable Control 0 = Timer0 clock Disabled. 1 = Timer0 clock Enabled.
[3]	TMR1_EN	Timer1 Clock Enable Control 0 = Timer1 clock Disabled. 1 = Timer1 clock Enabled.
[4]	TMR2_EN	Timer2 Clock Enable Control 0 = Timer2 clock Disabled. 1 = Timer2 clock Enabled.
[5]	TMR3_EN	Timer3 Clock Enable Control 0 = Timer3 clock Disabled. 1 = Timer3 clock Enabled.
[6]	FDIV_EN	Frequency Divider Output Clock Enable Control 0 = FDIV clock Disabled. 1 = FDIV clock Enabled.
[8]	I2C0_EN	I2C0 Clock Enable Control 0 = I2C0 clock Disabled. 1 = I2C0 clock Enabled.
[9]	I2C1_EN	I2C1 Clock Enable Control 0 = I2C1 clock Disabled. 1 = I2C1 clock Enabled.
[12]	SPI0_EN	SPI0 Clock Enable Control 0 = SPI0 clock Disabled. 1 = SPI0 clock Enabled.
[13]	SPI1_EN	SPI1 Clock Enable Control 0 = SPI1 clock Disabled. 1 = SPI1 clock Enabled.
[14]	SPI2_EN	SPI2 Clock Enable Control 0 = SPI2 clock Disabled. 1 = SPI2 clock Enabled.
[16]	UART0_EN	UART0 Clock Enable Control 0 = UART0 clock Disabled. 1 = UART0 clock Enabled.
[17]	UART1_EN	UART1 Clock Enable Control 0 = UART1 clock Disabled. 1 = UART1 clock Enabled.
[20]	PWM01_EN	PWM_01 Clock Enable Control 0 = PWM01 clock Disabled. 1 = PWM01 clock Enabled.
[21]	PWM23_EN	PWM_23 Clock Enable Control 0 = PWM23 clock Disabled. 1 = PWM23 clock Enabled.
[27]	USBD_EN	USB 2.0 FS Device Controller Clock Enable Control 0 = USB clock Disabled. 1 = USB clock Enabled.
[28]	ADC_EN	Analog-Digital-Converter (ADC) Clock Enable Control 0 = ADC clock Disabled. 1 = ADC clock Enabled.
[29]	I2S_EN	I2S Clock Enable Control 0 = I2S clock Disabled. 1 = I2S clock Enabled.
[31]	PS2_EN	PS/2 Clock Enable Control 0 = PS/2 clock Disabled. 1 = PS/2 clock Enabled.

Definition at line 763 of file NUC123.h.

CLK_T::APBDIV

Offset: 0x2C APB Divider Control Register

Bits	Field	Descriptions
[0]	APBDIV	APB Divider Enable Bit 0 = PCLK is HCLK. 1 = PCLK is HCLK/2.

Definition at line 772 of file NUC123.h.

CLK_T::CLKDIV

Offset: 0x18 Clock Divider Number Register

Bits	Field	Descriptions
[3:0]	HCLK_N	HCLK Clock Divide Number From HCLK Clock Source HCLK clock frequency = (HCLK clock source frequency) / (HCLK_N + 1).
[7:4]	USB_N	USB Clock Divide Number From PLL Clock USB clock frequency = (PLL frequency) / (USB_N + 1).
[11:8]	UART_N	UART Clock Divide Number From UART Clock Source UART clock frequency = (UART clock source frequency) / (UART_N + 1).
[23:16]	ADC_N	ADC Clock Divide Number From ADC Clock Source ADC clock frequency = (ADC clock source frequency) / (ADC_N + 1).

Definition at line 767 of file NUC123.h.

CLK_T::CLKSEL0

Offset: 0x10 Clock Source Select Control Register 0

Bits	Field	Descriptions
[2:0]	HCLK_S	HCLK Clock Source Select (Write Protect) The 3-bit default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b. 000 = Clock source from external 4~24 MHz high speed crystal oscillator clock. 001 = Clock source from PLL/2 clock. 010 = Clock source from PLL clock. 011 = Clock source from internal 10 kHz low speed oscillator clock. 111 = Clock source from internal 22.1184 MHz high speed oscillator clock. Note1: Before clock switching, the related clock sources (both pre-select and new-select) must be turn on. Note2: These bits are write protected bit. Refer to the REGWRPROT register.
[5:3]	STCLK_S	Cortex-M0 SysTick Clock Source Select (Write Protect) If SYST_CSR[2] = 1, SysTick clock source is from HCLK. If SYST_CSR[2] = 0, SysTick clock source is defined by STCLK_S(CLKSEL0[5:3]). 000 = Clock source from external 4~24 MHz high speed crystal clock. 010 = Clock source from external 4~24 MHz high speed crystal clock/2. 011 = Clock source from HCLK/2. 111 = Clock source from internal 22.1184 MHz high speed oscillator clock/2. Note1: If SysTick clock source is not from HCLK (i.e. SYST_CSR[2] = 0), SysTick clock source must less than or equal to HCLK/2. Note2: These bits are write protected bit. Refer to the REGWRPROT register.

Definition at line 765 of file NUC123.h.

CLK_T::CLKSEL1

Offset: 0x14 Clock Source Select Control Register 1

Bits	Field	Descriptions
[1:0]	WDT_S	Watchdog Timer Clock Source Select (Write Protect) 10 = Clock source from HCLK/2048 clock. 11 = Clock source from internal 10 kHz low speed oscillator clock. Note: These bits are write protected bit. Refer to the REGWRPROT register.
[3:2]	ADC_S	ADC Clock Source Select 00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. 01 = Clock source from PLL clock. 10 = Clock source from HCLK. 11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
[4]	SPI0_S	SPI0 Clock Source Selection 0 = Clock source from PLL clock. 1 = Clock source from HCLK.
[5]	SPI1_S	SPI1 Clock Source Selection 0 = Clock source from PLL clock. 1 = Clock source from HCLK.
[6]	SPI2_S	SPI2 Clock Source Selection 0 = Clock source from PLL clock. 1 = Clock source from HCLK.
[10:8]	TMR0_S	TIMER0 Clock Source Selection 000 = Clock source from external 4~24 MHz high speed crystal clock. 010 = Clock source from HCLK. 011 = Clock source from external trigger. 101 = Clock source from internal 10 kHz low speed oscillator clock. 111 = Clock source from internal 22.1184 MHz high speed oscillator clock. Others = Reserved.
[14:12]	TMR1_S	TIMER1 Clock Source Selection 000 = Clock source from external 4~24 MHz high speed crystal clock. 010 = Clock source from HCLK. 011 = Clock source from external trigger. 101 = Clock source from internal 10 kHz low speed oscillator clock. 111 = Clock source from internal 22.1184 MHz high speed oscillator clock. Others = Reserved.
[18:16]	TMR2_S	TIMER2 Clock Source Selection 000 = Clock source from external 4~24 MHz high speed crystal clock. 010 = Clock source from HCLK. 011 = Clock source from external trigger. 101 = Clock source from internal 10 kHz low speed oscillator clock. 111 = Clock source from internal 22.1184 MHz high speed oscillator clock. Others = Reserved.
[22:20]	TMR3_S	TIMER3 Clock Source Selection 000 = Clock source from external 4~24 MHz high speed crystal clock. 010 = Clock source from HCLK. 011 = Reserved. 101 = Clock source from internal 10 kHz low speed oscillator clock. 111 = Clock source from internal 22.1184 MHz high speed oscillator clock. Others = Reserved.
[25:24]	UART_S	UART Clock Source Selection 00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. 01 = Clock source from PLL clock. 11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
[29:28]	PWM01_S	PWM0 and PWM1 Clock Source Selection PWM0 and PWM1 used the same clock source; both of them used the same prescaler. The clock source of PWM0 and PWM1 is defined by PWM01_S (CLKSEL1[29:28]) and PWM01_S_E (CLKSEL2[8]). If PWM01_S_E = 0, the clock source of PWM0 and PWM1 defined by PWM01_S list below: 00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. 10 = Clock source from HCLK. 11 = Clock source from internal 22.1184 MHz high speed oscillator clock. If PWM01_S_E = 1, the clock source of PWM0 and PWM1 defined by PWM01_S list below: 00 = Reserved. 01 = Reserved. 10 = Reserved. 11 = Clock source from internal 10 kHz low speed oscillator clock.
[31:30]	PWM23_S	PWM2 and PWM3 Clock Source Selection PWM2 and PWM3 used the same clock source; both of them used the same prescaler. The clock source of PWM2 and PWM3 is defined by PWM23_S (CLKSEL1[31:30]) and PWM23_S_E (CLKSEL2[9]). If PWM23_S_E = 0, theclock source of PWM2 and PWM3 defined by PWM23_S list below: 00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. 10 = Clock source from HCLK. 11 = Clock source from internal 22.1184 MHz high speed oscillator clock. If PWM23_S_E = 1, the clock source of PWM2 and PWM3 defined by PWM23_S list below: 00 = Reserved. 01 = Reserved. 10 = Reserved. 11 = Clock source from internal 10 kHz low speed oscillator clock.

Definition at line 766 of file NUC123.h.

CLK_T::CLKSEL2

Offset: 0x1C Clock Source Select Control Register 2

Bits	Field	Descriptions
[1:0]	I2S_S	I2S Clock Source Selection 00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. 01 = Clock source from PLL clock. 10 = Clock source from HCLK. 11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
[3:2]	FRQDIV_S	Clock Divider Clock Source Selection 00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. 10 = Clock source from HCLK. 11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
[8]	PWM01_S_E	PWM0 and PWM1 Clock Source Selection Extend PWM0 and PWM1 used the same clock source; both of them used the same prescaler. The clock source of PWM0 and PWM1 is defined by PWM01_S (CLKSEL1[29:28]) and PWM01_S_E (CLKSEL2[8]). If PWM01_S_E = 0, the clock source of PWM0 and PWM1 defined by PWM01_S list below: 00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. 10 = Clock source from HCLK. 11 = Clock source from internal 22.1184 MHz high speed oscillator clock. If PWM01_S_E = 1, the clock source of PWM0 and PWM1 defined by PWM01_S list below: 00 = Reserved. 01 = Reserved. 10 = Reserved. 11 = Clock source from internal 10 kHz low speed oscillator clock.
[9]	PWM23_S_E	PWM2 and PWM3 Clock Source Selection Extend PWM2 and PWM3 used the same clock source; both of them used the same prescaler. The clock source of PWM2 and PWM3 is defined by PWM23_S (CLKSEL1[31:30]) and PWM23_S_E (CLKSEL2[9]). If PWM23_S_E = 0, the clock source of PWM2 and PWM3 defined by PWM23_S list below: 00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. 10 = Clock source from HCLK. 11 = Clock source from internal 22.1184 MHz high speed oscillator clock. If PWM23_S_E = 1, the clock source of PWM2 and PWM3 defined by PWM23_S list below: 00 = Reserved. 01 = Reserved. 10 = Reserved. 11 = Clock source from internal 10 kHz low speed oscillator clock.
[17:16]	WWDT_S	Window Watchdog Timer Clock Source Selection 10 = Clock source from HCLK/2048 clock. 11 = Clock source from internal 10 kHz low speed oscillator clock.

Definition at line 768 of file NUC123.h.

CLK_T::CLKSTATUS

Offset: 0x0C Clock status monitor Register

Bits	Field	Descriptions
[0]	XTL12M_STB	External 4~24 MHz High Speed Crystal (HXT) Clock Source Stable Flag (Read Only) 0 = External 4~24 MHz high speed crystal clock (HXT) is not stable or disabled. 1 = External 4~24 MHz high speed crystal clock (HXT) is stable and enabled.
[2]	PLL_STB	Internal PLL Clock Source Stable Flag (Read Only) 0 = Internal PLL clock is not stable or disabled. 1 = Internal PLL clock is stable in normal mode.
[3]	OSC10K_STB	Internal 10 KHz Low Speed Oscillator (LIRC) Clock Source Stable Flag (Read Only) 0 = Internal 10 kHz low speed oscillator clock (LIRC) is not stable or disabled. 1 = Internal 10 kHz low speed oscillator clock (LIRC) is stable and enabled.
[4]	OSC22M_STB	Internal 22.1184 MHz High Speed Oscillator (HIRC) Clock Source Stable Flag (Read Only) 0 = Internal 22.1184 MHz high speed oscillator (HIRC) clock is not stable or disabled. 1 = Internal 22.1184 MHz high speed oscillator (HIRC) clock is stable and enabled.
[7]	CLK_SW_FAIL	Clock Switching Fail Flag This bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1. 0 = Clock switching success. 1 = Clock switching failure. Note1: On NUC123xxxANx, this bit can be cleared to 0 by software writing "1". Note2: On NUC123xxxAEx, this bit is read only. After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLK_SW_FAIL will be cleared automatically by hardware.

Definition at line 764 of file NUC123.h.

CLK_T::FRQDIV

Offset: 0x24 Frequency Divider Control Register

Bits	Field	Descriptions
[3:0]	FSEL	Divider Output Frequency Selection Bits The formula of output frequency is Fout = Fin/2(N+1). Fin is the input clock frequency. Fout is the frequency of divider output clock. N is the 4-bit value of FSEL[3:0].
[4]	DIVIDER_EN	Frequency Divider Enable Bit 0 = Frequency Divider function Disabled. 1 = Frequency Divider function Enabled.

Definition at line 770 of file NUC123.h.

CLK_T::PLLCON

Offset: 0x20 PLL Control Register

Bits	Field	Descriptions
[8:0]	FB_DV	PLL Feedback Divider Control Bits Refer to the PLL formulas.
[13:9]	IN_DV	PLL Input Divider Control Bits Refer to the PLL formulas.
[15:14]	OUT_DV	PLL Output Divider Control Bits Refer to the PLL formulas.
[16]	PD	Power-down Mode If the PWR_DOWN_EN bit is set to 1 in PWRCON register, the PLL will enter Power-down mode too. 0 = PLL is in Normal mode. 1 = PLL is in Power-down mode (default).
[17]	BP	PLL Bypass Control 0 = PLL is in Normal mode (default). 1 = PLL clock output is same as PLL source clock input.
[18]	OE	PLL OE (FOUT Enable) Control 0 = PLL FOUT Enabled. 1 = PLL FOUT is fixed low.
[19]	PLL_SRC	PLL Source Clock Selection 0 = PLL source clock from external 4~24 MHz high speed crystal. 1 = PLL source clock from internal 22.1184 MHz high speed oscillator.

Definition at line 769 of file NUC123.h.

CLK_T::PWRCON

Offset: 0x00 System Power-down Control Register

Bits	Field	Descriptions
[0]	XTL12M_EN	External 4~24 MHz High Speed Crystal Enable (HXT) Control (Write Protect) The bit default value is set by flash controller user configuration register CFOSC (Config0[26:24]). When the default clock source is from external 4~24 MHz high speed crystal, this bit is set to 1 automatically. 0 = External 4~24 MHz high speed crystal oscillator (HXT) Disabled. 1 = External 4~24 MHz high speed crystal oscillator (HXT) Enabled. Note: This bit is write protected bit. Refer to the REGWRPROT register.
[2]	OSC22M_EN	Internal 22.1184 MHz High Speed Oscillator (HIRC) Enable Control (Write Protect) 0 = Internal 22.1184 MHz high speed oscillator (HIRC) Disabled. 1 = Internal 22.1184 MHz high speed oscillator (HIRC) Enabled. Note: This bit is write protected bit. Refer to the REGWRPROT register.
[3]	OSC10K_EN	Internal 10 KHz Low Speed Oscillator (LIRC) Enable Control (Write Protect) 0 = Internal 10 kHz low speed oscillator (LIRC) Disabled. 1 = Internal 10 kHz low speed oscillator (LIRC) Enabled. Note: This bit is write protected bit. Refer to the REGWRPROT register.
[4]	PD_WU_DLY	Wake-up Delay Counter Enable Control (Write Protect) When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable. The delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz high speed crystal, and 256 clock cycles when chip work at internal 22.1184 MHz high speed oscillator. 0 = Clock cycles delay Disabled. 1 = Clock cycles delay Enabled. Note: This bit is write protected bit. Refer to the REGWRPROT register.
[5]	PD_WU_INT_EN	Power-Down Mode Wake-Up Interrupt Enable Control (Write Protect) 0 = Power-down mode wake-up interrupt Disabled. 1 = Power-down mode wake-up interrupt Enabled. Note1: The interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high. Note2: This bit is write protected bit. Refer to the REGWRPROT register.
[6]	PD_WU_STS	Power-down Mode Wake-Up Interrupt Status Set by "Power-down wake-up event", it indicates that resume from Power-down mode. The flag is set if the GPIO, USB, UART, WDT, TIMER, I2C or BOD wake-up occurred. This bit can be cleared to 0 by software writing "1". Note: This bit is working only if PD_WU_INT_EN (PWRCON[5]) set to 1.
[7]	PWR_DOWN_EN	System Power-down Enable Bit (Write Protect) When this bit is set to 1, Power-down mode is enabled and chip Power-down behavior will depends on the PD_WAIT_CPU bit (a) If the PD_WAIT_CPU is 0, then the chip enters Power-down mode immediately after the PWR_DOWN_EN bit set. (b) if the PD_WAIT_CPU is 1, then the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode (recommend) When chip wakes up from Power-down mode, this bit is cleared by hardware. User needs to set this bit again for next Power-down. In Power-down mode, 4~24 MHz external high speed crystal oscillator (HXT) and the 22.1184 MHz internal high speed RC oscillator (HIRC) will be disabled in this mode, but the 10 kHz internal low speed RC oscillator (LIRC) is not controlled by Power-down mode. In Power- down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from the 10 kHz internal low speed RC oscillator (LIRC). The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from the internal 10 kHz low speed oscillator. 0 = Chip operating normally or chip in Idle mode because of WFI command. 1 = Chip enters Power-down mode instantly or waits CPU sleep command WFI. Note: This bit is write protected bit. Refer to the REGWRPROT register.
[8]	PD_WAIT_CPU	This Bit Control The Power-Down Entry Condition (Write Protect) 0 = Chip enters Power-down mode when the PWR_DOWN_EN bit is set to 1. 1 = Chip enters Power-down mode when the both PD_WAIT_CPU and PWR_DOWN_EN bits are set to 1 and CPU run WFI instruction. Note: This bit is write protected bit. Refer to the REGWRPROT register.

Definition at line 761 of file NUC123.h.

__I uint32_t CLK_T::RESERVE0

Definition at line 771 of file NUC123.h.

The documentation for this struct was generated from the following file:

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Data Fields